1. Field of the Invention
The present invention relates to a cache memory system and a method of accessing multiple items from a memory, particularly a memory which has cache memories associated with it.
2. Discussion of the Related Art
It is known in the art to provide a cache memory as a level of memory hierarchy between a central processing unit CPU or other main processor or memory master, and a main memory (or other memory-mapped device). A cache memory duplicates commonly-used locations in a main memory for the purpose of speeding up accesses to these locations. In general it stores the most recently used instructions or data from the larger but slower main memory. This means that when the CPU wishes to access data or instructions, the access request can be made to the cache instead of to the main memory. This takes far less time than an access to a main memory, thus the CPU can read or write data more quickly and consequently runs more efficiently than if a cache memory were not used. The cache also updates the main memory with the duplicated locations when required, explicitly or implicitly.
Since computer programs frequently use a subset of instructions or data repeatedly, the cache is a cost effective method of enhancing the memory system in a “statistical” method, without having to resort to the expense of making all of the memory system faster.
The cache is usually smaller than the main memory, which means that it cannot provide a duplicate of every location. Therefore, when an access request in the form of an address is made to the cache, it needs to determine if that particular location currently being requested is one of those duplicated locally or whether it needs to be fetched from the main memory, i.e. it performs a “tag compare” to see if that item is present in the cache. If the location is already stored in the cache, the access is termed a “hit” and if it is not it is termed a “miss”. The determining of whether an access is a hit or a miss takes an amount of time, thit. This time is normally the main factor in the amount of time that the cache takes to return a frequently used location and since speed is the purpose of such operations, this is designed to be as short as possible.
If the item is present (“hit”) it is returned quickly to the requesting CPU or the like. If however the item is not found (“miss”) then it is fetched from the main memory and may be stored into the cache.
As a result of processor performance requirements it is now not uncommon for processors (or the like) to execute more than one operation per cycle and as a result, it is often the case that more than one item is required to be read from main memory during a clock cycle. Consequently multiple accesses need to be made to the cache memory during one clock cycle in order to supply data and/or instructions at the rate required by the program that the processor is running. Clearly this is not possible if a single cache memory with a single port is used.
One known solution is for a cache memory to have multiple ports to the same data. Thus, each time an item is required, it can be looked for simultaneously at each port. The provision of multiple ports also allows several items to be looked for simultaneously in the cache memory. One problem with this solution is that significantly more memory space is required than in the multiple-cache system, leading to greater manufacturing expense and operating power.
Another known solution is to use multiple cache memories, each with their own port. This does allow large quantities of data and/or instructions to be accessed at the same time. However, one problem with such a system is that it is necessary to know from which cache memory to access particular items. This is achieved in the coding of the program being run, which means that the coding is far more complicated than it would otherwise be. Furthermore, the coding necessarily needs to be system-specific because the extra code to deal with the access requirements needs to be based on the structure of the cache memory system being accessed. Another problem is that of aliasing i.e. the same item appearing in more than one cache memory. The aliasing problem is of concern when it comes to writing back to the main memory and is complicated to solve since the cache memories are distinct from one another.
It would therefore be desirable to provide means for allowing multiple accesses to a cache which minimizes special coding requirements and is not system-specific. It would further be desirable to achieve such a system without significantly increasing cache memory size and which would also deal with aliasing.